Memory devices are commonly employed as internal storage areas in a computer or other type of electronic equipment. One specific type of memory used to store data in a computer is random access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM), for example. RAM is typically used as main memory in a computer environment. RAM is generally volatile, in that once power is turned off, all data stored in the RAM is lost.
A typical SRAM device includes an array of individual SRAM cells. Each SRAM cell is capable of storing a binary voltage value therein, which voltage value represents a logical data bit (e.g., “0” or “1”). One existing configuration for an SRAM cell includes a pair of cross-coupled devices such as inverters. With complementary metal oxide semiconductor (CMOS) technology, the inverters further include a pull-up PFET (p-channel) transistor connected to a complementary pull-down NFET (n-channel) transistor. The inverters, connected in a cross-coupled configuration, act as a latch that stores the data bit therein so long as power is supplied to the memory array. In a conventional six-transistor (6T) cell, a pair of access transistors or pass gates (when activated by a word line) selectively couples the inverters to a pair of complementary bit lines. Other SRAM cell designs may include a different number of transistors, e.g., 4T, 8T, etc.
The design of SRAM cells has traditionally involved a compromise between the read and write functions of the memory cell to maintain cell stability, read performance, and write performance. The transistors which make up the cross-coupled latch must be weak enough to be overdriven during a write operation, while also strong enough to maintain their data value when driving a bit line during a read operation. The access transistors that connect the cross-coupled cell nodes to the true and complement bit lines affect both the stability and performance of the cell. In one-port SRAM cells, a single pair of access transistors is conventionally used for both read and write access to the cell. The gates are driven to a digital value in order to switch the access transistors between an on and off state. The optimization of an access for a write operation would drive the reduction of the on-resistance (Ron) for the device. On the other hand, the optimization of an access transistor for a read operation drives an increase in Ron in order to isolate the cell from the bit line capacitance and prevent a cell disturb.
One approach to improving write performance of SRAM devices is to use so-called “negative boosting” to discharge a bit line to a voltage level below the nominal low supply rail value (e.g., ground). In so doing, the access transistors or pass gates of the SRAM cell coupled to the discharged bit line see a resultant increase in both the gate-to-source and drain-to-source voltages. This negative boosting facilitates internal node discharge and flipping of the cross-coupled latch as compared to more conventional write techniques in which the bit line is simply discharged to the value of the nominal low voltage rail (e.g., ground).